1. Field of the Invention
This invention relates generally to simulation of digital logic systems and, more particularly, to the processing of wire delay values for nets within digital logic systems that are being simulated.
2. Description of the Related Art
Digital logic simulation refers to computer-aided design of complicated logic networks in which a software model of a logic network is supported so that a set of inputs can be provided to the software model and the output of the model can be obtained to confirm the desired operation. In addition, many digital logic simulation systems permit the performance of the logic network to be studied. That is, the time needed for a signal to propagate through the logic network can be simulated and evaluated. Most digital logic simulation systems are designed to operate in a host mainframe computer system or workstation environment.
The logic network being simulated comprises a digital logic circuit whose components are modelled as blocks that receive input logic data values from one or more input pins and produce output values based on the input, and provide the output values to one or more output pins. Blocks can represent latched components that operate in accordance with a clock signal, such as multiplexers and flip-flops, or blocks can represent combinational logic elements, such as AND gates and OR gates, or the blocks can represent operational circuits, such as processor units and arithmetic logic units. Just as the digital logic circuit components are connected to each other by wires, the simulation blocks of the software model are "connected" to other blocks by nets.
Some logic simulation systems permit the modelling of delay times through logic circuit components, wherein the model considers a delay time comprising the time necessary for an input value to propagate through a circuit component. In the design of relatively complex digital systems that operate at high digital signal frequencies, it can be important to consider delay times due to the time necessary for a logic value to propagate over a wire connecting one component to another. The propagation time can vary dramatically because the length of a connecting wire can vary dramatically. For example, the length of a connection between two components located on the same circuit chip can be on the order of microns, while the length of a connection extending between two different chips can be on the order of millimeters, which is equal to thousands of microns. The logic value propagation times can vary accordingly and can become significant at high signal frequencies.
The performance of logic simulation systems can vary greatly in terms of processing time, data requirements, computer hardware support requirements, and the like. In the case of logic simulation systems that support modelling of wire delays, simulation performance and capabilities can vary greatly. For example, some systems permit only wire delay values of a fixed duration. As noted above, wire delays for connections can vary greatly. Modelling wire delays with fixed duration delay times can result in inaccurate simulation performance. Alternatively, such systems might need to model variable wire delays with multiple nets connected serially. The performance penalty for modelling a string of wire delay nets can be severe.
In addition to variations in the fidelity of wire delay modelling, performance also can be greatly reduced when wire delays are being modeled. That is, some logic simulation systems incur a significant increase in execution time when wire delays are modelled as compared to execution time without wire delays. For example, a digital logic circuit being modelled can include hundreds of thousands of components. The simulation blocks would be correspondingly connected by hundreds of thousands of nets, potentially requiring the specification of thousands of wire delay values that must be considered during the simulation. Such additional processing as compared with systems that do not model wire delays can comprise a significant performance penalty.
From the discussion above, it should be apparent that there is a need for a logic simulation system that supports wire delays that accurately reflect values of the logic circuit being modelled without incurring a significant performance penalty. The present invention satisfies this need.